1. Technical Field of the Invention
The present invention relates to semiconductor devices, and more specifically, it relates to a semiconductor device with a non-volatile memory.
2. Description of the Related Art
In order to write data on a non-volatile memory such as a flash memory, a high voltage of 12 to 18 V is necessary. Since the supply voltage of recent semiconductor devices ranges from 3 to 5 V, it is necessary to boost the supply voltage of semiconductor devices in order to obtain a high enough voltage to drive the non-volatile memory. In a normal mode, a built-in charge pump circuit in the semiconductor device is generally used to obtain high voltages. In contrast, in a check mode in which the operation of the semiconductor device is checked, the operation of each circuit portion must be checked. It is therefore necessary to supply a high voltage from the outside.
In FIG. 3, an example of the structure of such a conventional semiconductor device is shown. As shown in FIG. 3, the semiconductor device includes a normal charge pump circuit 11 for generating a high voltage in order to write data on a non-volatile memory in a normal mode. The output voltage of the normal charge pump circuit 11 is stabilized by a regulator 2, and the voltage is supplied to an internal circuit 3 which includes the non-volatile memory. In contrast, when performing a writing test to write to the non-volatile memory in a test mode, a test enable signal becomes active, and a high voltage is applied to a high voltage feeding terminal 4. When the test enable signal becomes active, the regulator 2 stops operating, and a testing charge pump circuit 12 starts boosting the voltage. In the test mode, the normal charge pump circuit 11 does not operate. The voltage boosted by the testing charge pump circuit 12 is applied to the gate of an N-channel MOS transistor QN6. Accordingly, the transistor QN6 is turned on, and the high voltage applied to the high voltage feeding terminal 4 is supplied to the internal circuit 3.
By providing the testing charge pump circuit 12 in addition to the normal charge pump circuit 11, the gate voltage of the transistor QN6 does not vary even when a high current flows through the internal circuit 3. Thus, it is possible to reliably control the on/off state of high voltage supplied from the outside. In contrast, there is a drawback in that the chip area of the semiconductor device is increased in order to provide the testing charge pump circuit 12.
In FIG. 4, another example of the structure of a conventional semiconductor device is shown. As shown in FIG. 4, the semiconductor device includes a high voltage switch 25 in place of the testing charge pump circuit 12 shown in FIG. 3. In a test mode, a high voltage HV is supplied from a charge pump circuit 1 to the high voltage switch 25, and the high voltage switch 25 starts operating. The output voltage of the high voltage switch 25 is applied to the gate of an N-channel MOS transistor QN6 which is used as a pass gate. Accordingly, the transistor QN6 is turned on, and the high voltage applied to the high voltage feeding terminal 4 is supplied to the internal circuit 3.
By providing the high voltage switch 25 which operates in response to the supply of a high voltage from the charge pump circuit 1, the testing charge pump circuit 12 shown in FIG. 3 can be omitted. In contrast, when a high current which exceeds the capacity of the charge pump circuit 1 flows through the internal circuit 3, the output voltage of the high voltage switch 25, that is, the gate voltage of the transistor QN6, decreases. It therefore becomes impossible to reliably control the on/off state of a high voltage.
Accordingly, it is an object of the present invention to provide a semiconductor device with a non-volatile memory, in which the on/off state of a high voltage supplied from the outside is reliably controlled, without increasing the chip area to a large extent.
In order to solve the foregoing problems, a semiconductor device according to the present invention is a semiconductor device with a non-volatile memory, including a charge pump circuit for generating a predetermined voltage in the semiconductor device; a voltage feeding terminal to which a voltage is applied from the outside; a first impedance device for switching on/off an electric current path between the charge pump circuit and the non-volatile memory; a second impedance device for switching on/off an electric current path between the voltage feeding terminal and the non-volatile memory; and a control circuit, to which the voltage is applied from the charge pump circuit, for controlling the first and second impedance devices.
The control circuit may include a switch circuit for turning off the first impedance device and turning on the second impedance device in accordance with a signal which becomes active in a test mode. The semiconductor device may further include a third impedance device controlled by the control circuit, the third impedance device switching on/off an electric current path between the charge pump circuit and the voltage feeding terminal. Also, the semiconductor device may further include a regulator for stabilizing the voltage supplied in a normal mode from the charge pump circuit to the non-volatile memory through the first impedance device.
According to the present invention, a semiconductor device with a non-volatile memory can reliably control the on/off state of a high voltage supplied from the outside, without increasing the chip area to a large extent.